This invention relates generally to memory cell circuits and more particularly, it relates to a biasing circuit for intermittent memories, such as a first-in first-out (FIFO) memory array, in which the bit lines in the array are continuously biased so as to compensate for leakage current without consuming any power.
In general, memories can suffer failures due to loss of data stored in cells when they do not have fixed cycle times. Assuming that such data stored in the memory cells are needed to be read, a read row line is typically activated so as to connect the memory cells to a pair of read bit-lines. Thus, the data stored in the cells will be transferred to the bit-lines. A failure may occur during this read cycle if leakage is present on the bit-lines. This is because all of the charges on the bit-lines and the memory cells could be leaked away, thereby resulting in a loss of data in the memory cells.
Since the problem of leakage is a relatively slow process as compared to the normal read access times, a failure will not occur if the read cycle ends quickly enough. Therefore, the leakage problem is only encountered by intermittent memories, such as FIFO memories, which allows the read cycle to occur over an indefinite amount of time.
There are known two prior art solutions to this problem. One approach is to cause the read cycle to end a fixed amount of time after the cycle begins. However, this requires the use of a clock or timing circuit inside the memory array to end the cycle. The internal clock for this approach is not only complex, but is sensitive to variations due to temperature, processing and supply voltage.
A second approach which has been employed on a 1k.times.9 deep FIFO memory is to actively bias the bit-lines with a pair of transistors, as shown in FIG. 1. These transistors N4, N5 are designed so as to supply more current to the bit-lines than can be leaked off. Unfortunately, the problem with this approach has been that one of the pair of transistors is biasing high the bit-line that the memory cell is holding "low" during the read cycle. As a result, there is provided a direct current path to ground which causes power dissipation. While this transistor can be made weak so as to minimize the power drain, this suffers from the disadvantage that the transistor must be made large, thereby increasing expense and occupying more chip area.
The present invention represents an improvement over the second approach in which only one of the pair of bit-lines is biased, the bit-line that the memory cell is holding "high" during the read cycle. The other bit-line that the memory cell is holding "low" is not biased at all. Thus, no power dissipation will occur.